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Title:
Image preprocessing for the infrared
Authors:
Scribner, Dean A.; Schuler, Jonathon M.; Warren, Penny; Howard, J. G.; Kruer, Melvin R.
Affiliation:
AA(Naval Research Lab.), AB(Naval Research Lab.), AC(Naval Research Lab.), AD(Naval Research Lab.), AE(Naval Research Lab.)
Publication:
Proc. SPIE Vol. 4028, p. 222-233, Infrared Detectors and Focal Plane Arrays VI, Eustace L. Dereniak; Robert E. Sampson; Eds. (SPIE Homepage)
Publication Date:
07/2000
Origin:
SPIE
Bibliographic Code:
2000SPIE.4028..222S

Abstract

The emergence of new infrared sensor technologies and the availability of powerful, inexpensive computers have made many new imaging applications possible. Researchers working in the area of traditional image processing are showing an increased interest in working with infrared imagery. However, because of the inherent differences between infrared and visible phenomenology, a number of fundamental problems arise when trying to apply traditional processing methods to the infrared. Furthermore, the technologies required to image in the infrared are currently much less mature than comparable camera technologies used in visible imaging. Also infrared sensors need to capture six to eight additional bits of additional dynamic range over the eight normally used for visible imaging. Over the past half-century, visible cameras have become highly developed and can deliver images that meet engineering standards compatible with image displays. Similar image standards are often not possible in the infrared for a number of technical and phenomenological reasons. The purpose of this paper is to describe some of these differences and discuss a related topic known as image preprocessing. This is an area of processing that roughly lies between traditional image processing and image generation; because the camera images are less than ideal, additional processing is needed to perform necessary functions such as dynamic range management, non-uniformity correction, resolution enhancement, or color processing. A long-range goal for the implementation of these algorithms is to move them on-chip as analog retina-like or cortical-like circuits, thus achieving extraordinary reductions in power dissipation, size, and cost. Because this area of research is relatively new and still evolving, the discussion in this paper is limited to only a partial overview of the topic.
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